Electrical Engineering

Head of Department

Dr. Sanjoy Debbarma
PhD (NIT Silchar)



Priyabrat Garanayak Research Scholars

M.Tech (Specialization: VLSI and Embedded Design), Centre for Microelectronics, BPUT, Odisha.

Full Time/Part Time Scholar: Full-Time
Professional Membership : IEEE Student Member, IET Member

Highest Degree with specialization(Name of Institute)

  • PhD (Specialization: Power System), National Institute of Technology Meghalaya, Shillong

Academic Honors & Awards:


Research Area:

  • Power System Harmonic Estimation
  • Design of Active and Hybrid Filters
  • Unified Power Quality Conditioner (UPQC)
  • Series-Parallel Uninterruptible Power Supply (SP-UPS)
  • Adaptive Signal Processing Application in Power System

Research Plan:

  • »View Research Plan

Dotoral Thesis:

  • »View Thesis

Seminar/Conference Attended :

  • P. Garanayak and G. Panda, “A novel current control technique to enhance dynamic performance of shunt active power filter", All India seminar on Recent Advances in Power, Energy and control (RAPEC-2013), NIT Rourkela, Nov. 2013.
  • P. Garanayak and G. Panda, “Review on power quality improvement in a distribution network using active power filters", National Seminar on Development of Smart Grid in India, NEHU Shillong, Nov. 2013.


  • P. Garanayak and G. Panda, “Fast and accurate measurement of harmonic parameters employing hybrid adaptive linear neural network and filtered-x least mean square algorithm”, IET Generation, Transmission & Distribution, vol. 10, no. 2, pp. 421-436, Feb. 2016. (SCI Journal, 2015 Impact Factor 1.576)
  • P. Garanayak, G. Panda, and P. K. Ray, “Harmonic estimation using RLS algorithm and elimination with improved current control technique based SAPF in a distribution network”, International Journal of Electrical Power & Energy Systems, vol. 73, pp. 209–217, Dec. 2015. (SCIE Journal, 2015 Impact Factor 2.587)
  • P. Garanayak and G. Panda, “Harmonic elimination and reactive power compensation by novel control algorithm based active power filter”, Journal of Power Electronics, vol. 15, no. 6, pp. 1619–1627, Nov. 2015. (SCIE Journal, 2015 Impact Factor 0.931)
  • P. Garanayak and G. Panda, “FPGA Based Shunt Hybrid Active Power Filter for Harmonic Mitigation”, 5th International Exhibition & Conference, New Technologies in Transmission, Distribution, Smart Grid & Communication (GRIDTECH-2015), pp. 560–567, New Delhi, Apr. 2015.
  • P. Garanayak, G. Panda and P. K. Ray, “Power System Harmonic Parameters Estimation using ADALINE-VLLMS Algorithm”, IEEE International Conference on Energy, Power and Environment: Towards Sustainable Growth (ICEPE 2015), pp. 1–6, NIT Meghalaya, Shillong, Jun. 2015.

Any other remarkable : Experience ::

  • Since August 2016, working as a Research Associate, department of Electrical Engineering, Indian Institute of Technology Delhi, India.
  • From September 2013 to December 2013, worked as a Junior Research Fellow, department of Electrical and Electronics Engineering, National Institute of Technology Meghalaya, Shillong, India.
  • From February 2013 to August 2013, worked as a Lecturer, department of Electronics & Telecommunication Engineering, Indira Gandhi Institute of Technology Sarang, Odisha, India.