Head of Department

Dr. Prabir Kumar Saha




Research Interest

Low power VLSI design, Cyclic combinational circuits, Content Addressable Memory (CAM), Memristor based memory Design, In-memory Computing.

Education Qualification

Ph.D, Jadavpur University


International Journals: (Last 10 years)

Total Publications: 96, J (48), C (48)


[48]      Shyamosree Goswami, Vikatakavi Chandana, Anup Dandapat, “An approach to design a low power high-speed full adder circuit based on logical effort” in the Electronics Journal, Accepted, Jan-2024.


[47]       S. W. HussainT. V. MahendraS. Mishra  ;  A. Dandapat, “SMS-CAM: Shared Matchline Scheme for Content Addressable Memory” in the  Integration the VLSI Journal, Elsevier. https://doi.org/10.1016/j.vlsi.2022.08.013 Vol-88, pp-70-79, Jan-2023.


[46]      Keshab Das,  A. Dandapat, ""Design of a 1.29-1.61 GHz LC-VCO with Improved Phase Noise and Figure-of Merit (FoMT) for GPS and Satellite Navigation" in the  Journal of Circuits, Systems, and Computers, Accepted-May  2022.


[45]         S. W. HussainT. V. MahendraS. Mishra  ;  A. Dandapat, ""Match-Line Control Unit for Power and Delay Reduction in Hybrid CAM" in the  IET Circuits, Devices & Systems, https://doi.org/10.1049/cds2.12024 , Vol-15, issue-3,  pp 272-283, Feb 2021.


[44]       S. W. HussainT. V. MahendraS. Mishra  ;  A. Dandapat, ""Low-Power Content Addressable Memory Design using Two-Layer P-N Match-Line Control and Sensing" in the  Integration the VLSI Journal, Elsevier. https://doi.org/ 10.1016/j.vlsi.2020.06.001  Vol 75, pp 73-84 Nov 2020.

[43]       T. V. MahendraS. W. HussainS. Mishra  ;  A. Dandapat, ""A Novel Low-Power Matchline Evaluation Technique for Content Addressable Memory (CAM)" in the  Special Issue On Advanced Networking And Communication Solutions For Wireless Mobile Networks, Journal of Information Science and Engineering, https://jise.iis.sinica.edu.tw/JISESearch/pages/View/PaperView.jsf?keyId=176_2357,  Vol. 36, no-5,  pp. 1035-1053 , Mar 2020.

[42]       T. V. MahendraS. W. HussainS. Mishra  ;  A. Dandapat, ""Energy-Efficient Precharge-Free Ternary Content Addressable Memory (TCAM) for High Search Rate Applications" in the IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, pp. 2345-2357,  DOI:10.1109/TCSI.2020.2978295, Feb 2020.

[41]        S. Mishra ; T. V. Mahendra ; S. W. Hussain ;  A. Dandapat, " Analogy of Matchline Sensing Techniques for Content Addressable Memory (CAM)' IET Computers & Digital Techniques, Vol. 14, pp. 87-96, DOI:10.1049/iet-cdt.2019.0178, Feb 2020,


[40]         T. V. Mahendra ; S. W. Hussain ; S. Mishra ; A. Dandapat, " Low Discharge Precharge Free Matchline Structure for Energy-Efficient Search using CAM, Integration the VLSI Journal, Elsevier. https://doi.org/10.1016/j.vlsi.2019.08.002 , Vol. 69, pp-31-39, 2019.

[39]       Farhana Begum, S. Mishra ;  A. Dandapat,, “Low Power 10-Bit Flash ADC with Divide and Collate Subranging Conversion Scheme”, Transactions on Computer Science & Engineering and Electrical Engineering, Scientia Irinica, DOI: 10.24200/SCI.2019.5162.1129, vol-28, issue-6, pp. 3464-3479 2019

[38]          Anup Dandapat, “Methodologies for CAM and ADC design”, CSI Transactions on ICT, Springer , vol. 7, pp-87-91, June 2019.

[37]       Farhana Begum, S. Mishra ;  Najrul Islam ; A. Dandapat,, “A 10-bit 2.33 fJ/conv. SAR-ADC with High Speed Capacitive DAC Switching using a Novel Effective Asynchronous Control Circuitry”, Analog Integrated Circuits and Signal Processing, Springer, https://doi.org/10.1007/s10470-019-01450-w , Volume 100, Issue 2, pp 311–325 , 2019.

[36]        Farhana Begum, S. Mishra ;  Najrul Islam ; A. Dandapat,, “Frequency Improvement of 10-bit SAR-ADC using TSPC based Control Circuitry”, IEEE VLSI Circuits & Systems Letter (VCAL), Vol-5, issue-1, pp-1-8, 2019.


[35]     S. W. HussainT. V. Mahendra ;  S. Mishra ; A. Dandapat,, “Match-Line Division and Control to Reduce Power Dissipation in Content Addressable Memory”, IEEE Transactions on Consumer Electronics, DOI: 10.1109/TCE.2018.2859623 Vol. 64, Issue 3, pp-301-309 , 2018.

[34]       Farhana Begum and Anup Dandapat, “A 10-bit 2.5 GS/s low power hybrid subranging flash-SAR ADC for high data rate communication”, CSI Transactions on ICT, Springer , May 2018, DOI 10.1007/s40012-018-0190-3.

[33]          T. V. Mahendra ; S. W. Hussain ; S. Mishra ; A. Dandapat, " Precharge Free Dynamic Content Addressable Memory, Electronics Letters, IET,  https://doi.org/10.1049/el.2018.0592  Vol-54, issue-9, pp 556-558, Mar 2018.


[32]       D. Kumar, P. Saha  and A. Dandapat , " Hardware Implementation of Methodologies of Fixed Point Division Algorithms, International Journal on Smart Sensing and Intelligent Systems, Vol-10, Issue-3, pp.630-645, Sep. 2017.

[31]         D. Kumar, P. Saha  and A. Dandapat , " Vedic Algorithm for Cubic Computation and VLSI Implementation" in the Engineering Science and Technology, Elsevier, Vol-20, Issue-5, 2017.

[30]         S. Mishra, T. V. Mahendra,  J. Saikia and A. Dandapat , " A Low-Overhead Dynamic TCAM with Pipelined Read-Restore Refresh Scheme" in the IEEE Transactions on Circuits and Systems I: Regular Papers., DOI: 10.1109/TCSI.2017.2756662 Vol-65, issue 5, pp 1591-1601, 2017. 

[29]         T. V. Mahendra, S. Mishra  and A. Dandapat , "Self Controlled High Performance Pre-Charge Free Content Addressable Memory”, in IEEE Transactions on Very Large Scale Integration Systems, DOI: 10.1109/TVLSI.2017.2685427 vol. 25, no. 08, pp. 2388-2392, 2017. 


[28]        S. Mishra and A. Dandapat, Energy-efficient adaptive match-line controller for large-scale associative storage, IEEE Transactions on Circuits and Systems II: Express Briefs,  DOI: 10.1109/TCSII.2016.2595598 Vol.-64, Issue No.-6, Page Nos -710-714, 2016.

[27]         S. Mishra, T. V. Mahendra, and A. Dandapat, A 9-T 833-MHz 1.72-fJ/bit/search quasi static ternary fully associative cache tag with selective matchline evaluation for wire speed applications, IEEE Transactions on Circuits and Systems I: Regular Papers, DOI: 10.1109/TCSI.2016.2592182, Vol. 63, Issue No. 11, Page Nos. 1910-1920, 2016. 

[26]       V. Kumar and A. Dandapat, Design Methodology for Multiple Output Combinational Circuits Using Cyclic Combinational Technique, Journal of Circuits, Systems, and Computers, https://doi.org/10.1142/S021812661650153X, Vol. 25, Issue No. 12, pp- 1650153-1-20, 2016.

[25]         V. Kumar, C. K. Jha, G. Thapa, and A. Dandapat, A Novel Methodology for Design of Cyclic Combinational Circuits, Journal of Low Power Electronics, Vol. 12, Issue No. 3, Page Nos. 205-217, 2016.


[24]         S. Mishra, A. Dandapat, “ EMDBAM: A Low Power Dual Bit Associative Memory with Match Error and Mask Control”, ” in IEEE Transactions on Very Large Scale Integration Systems, DOI: 10.1109/TVLSI.2015.2503005, vol. 24, no. 6, pp. 2142-2151, 2015.

[23]         Partha Bhattacharyya, B. Kundu, S. Ghosh, Vinay Kumar, and A. Dandapat,  “Performance Analysis of a Low Power High Speed Hybrid 1 Bit Full Adder Circuit” in IEEE Transactions on Very Large Scale Integration Systems, DOI: 10.1109/TVLSI.2014.2357057, vol. 23, issue 10, pp. 2001-2008, 2015.


[22]     P. Saha, D. Kumar, P. Bhattacharyya, A. Dandapat, “Design of 64-Bit Squarer Based On Vedic Mathematics” in Journal of Circuits, Systems, and Computers, World Scientific, https://doi.org/10.1142/S0218126614500923,  vol. 23, pp- 1450092, 2014.

[21]      P. Saha, D. Kumar, P. Bhattacharyya, A. Dandapat., “Vedic Division Methodology for High Speed VLSI Applications"  in IET Journal of Engineering, pp. 1-9, 2014.

[20]      P. Saha, P. Bhattacharyya, A. Dandapat, “improved floating point multiplier design based on canonical sign digit”, in International journal of Technology, Vol. 5, No 1, pp. 22-31, 2014.

[19]       D. KayalP. MostafaA. DandapatC. K. Sarkar, “Design of High Performance 8 bit Multiplier using Vedic Multiplication Algorithm with McCMOS Technique”, in The Journal of Signal Processing Systems, Springer, https://doi.org/10.1007/s11265-013-0818-3, Vol. 76, Issue-1, pp. 1-9, Accepted, July-2013, published-2014.

[18]      P. Saha, A. Banerjee, P. Bhattacharyya, A. Dandapat*, “Improved Matrix Multiplier Design for High Speed DSP Applications”,  in IET journal of Circuits, Devices & Systems, https://doi.org/10.1049/iet-cds.2013.0117 vol. 8, issue 1, pp. 27-37, 2014.


[17]      D. Ghosh1, P. C. Mondal1, D. Kayal2, P. Bhattacharyya1, A. Dandapat, “A Novel Design of Seven Segment Decoder using Cyclic Combinational Technique”, in International Journal of Low Power Electronics, ASP, vol. 9, No 4, pp. 421-426, 2013.

[16]        P. Saha, A. Banerjee, P. Bhattacharyya, A. Dandapat “A High Speed Multiplier using High Accuracy Floating Point Logarithmic Number System",  in Trans. on Computer Sc. & Engineering & Electrical Engineering, Science and Technology, scientia Iranica, vol. 21, No 3, pp. 826-841, 2013.


 [15]        D. Kayal, A. Dandapat, “Design of a High Performance Memory Using a Novel Architecture of Double Bit CAM and SRAM”  in International Journal of Electronics, Tailor & Francis,   https://doi.org/10.1080/00207217. 2012.681530,   Vol. 99, Issue: 12, pp. 1691-1702, 2012.

[14]      M. Chanda, A. S. Chakraborty, A. Dandapat and H. Rahaman, “pre-settable sequential circuits design using single-clocked energy efficient adiabatic logic”, in Journal of Electron Devices, Vol. 12, 2012, pp. 713-718, 2012.


[13]      Prabir Kumar Saha, A. Dandapat, P. Bhattacharrya, “ASIC Design of a High Speed Low Power Circuit for Factorial Calculation Using Ancient Vedic Mathematics” in Microelectronics Journal, Elsevier. https://doi.org/10.1016/j.mejo.2011.09.001 Vol. 42 (2011) , pp.1343–1352, 2011.

[12]     Prabir Saha, A. Dandapat and P. Bhattacharrya, “ASIC Implementation of High Speed Processor for Calculating Discrete Fourier Transformation using Circular Convolution Technique” in WSEAS Trans. on Circuits and Systems. Issue 8, Volume 10, August 2011.

[11]        S. Mukherjee, P. Mustafa, D. Kayal, A. Dandapat and C. K. Sarkar, “Flash Type ADC Using Input Voltage Level Based Circuit Activation Technique” in International Journal of Electronics & Telecommunication And Instrumentation Engineering, PP[23?29], Volume 06, Issue No 01, December 2011.

[10]      Prabir Saha, Arindam Banerjee, A. Dandapat and P. Bhattacharrya “Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processors”, in international Journal of smart sensing and intelligent systems, vol. 4, no. 2, pp 268-284, June, 2011.

International Conferences: (Last 10 years)

Total Publications: 96, J (48), C (48)


[48]      S. Goswami , K.H.Varma , R.Gudla , A Dandapat, “CASCAM: Comparative Analysis of Search operation of FinFET and MOSFET based Content Addressable Memory (CAM)”, 3rd International Symposium on Sustainable Energy and Technological Advancements (ISSETA 2024), National Institute of Technology Meghalaya, India,23rd -24th  Feb. 2024.

[47]       Shyamosree Goswami, Alok Kumar and Anup Dandapat, “Design of a Stack Based Compressor for High Speed Computation”, 2024 IEEE 9th International Conference for Convergence in Technology (I2CT), VIVANTA PUNE, HINJAWADI (Hinjewadi) Pune (Maharashtra) ,India. , 5th-7th Apr 2024.


[46]     A. DuttaGupta, S.Goswami, A. Dandapat, “Low Power Sense Amplifier For A 64×32 Bit Sram Array For Iot Application”, 2023 4th International Conference on Computing and Communication Systems (I3CS), NEHU, Meghalaya, India, 16th-18th Mar 2023


[45]      V. Kuwal, S. S. Yadav, and A. Dandapat, "Analysis of the Universal Gates based on the comparative factors of Delay Propagation, Average Power dissipation, and Logical Effort"in IEEE 2nd International Conference of Emerging Technology, Belgaum, India, May 2021.

[44]      M. Saha and A. Dandapat, "Modified Baugh Wooley Multiplier using Low Power Compressors," 2021 IEEE International Conference of Emerging Technologies (INCET), Belgaum, India, 2021

[43]     S. W. Hussain and A. Dandapat, "Match-Line Controlled Content Addressable Memory: Low-Power and High-Speed Searching", in Student Research Forum of  IEEE 34th International Conference on VLSI Design & 20th International Conference on Embedded Systems (VLSID) 2021, India (Virtual),  2021


[42]  S. W. Hussain ,T. V. Mahendra, S. Mishra, and A. Dandapat, " Efficient Matchline Controller for Hybrid Content Addressable               Memory ”, in IEEE region 10 SYMPOSIUM (TENSYMP) 2020 5th – 7th June, 2020 | Dhaka, Bangladesh.


[41]        T. V. Mahendra, S. W. Hussain, S. Mishra, and A. Dandapat, " A Low-Power Split Controlled Single Ended Storage Content Addressable Memory ”, in IEEE International Symposium on Smart Electronic Systems (IEEE-iSES), on 16-18 December 2019, Rourkela, India

[40]     T. V. Mahendra, S. W. Hussain, S. Mishra, and A. Dandapat, " Design and Implementation of Drivers and Selectors for Content Addressable Memory (CAM) ”, in 2nd International Conference on Electronics and Communication Engineering (ICECE’2019), on 9-11 December 2019, Xi'an, China.

[39]      S. W. Hussain ,T. V. Mahendra, S. Mishra, and A. Dandapat, " Efficient Matchline Controller for Hybrid Content Addressable Memory ”, in 2nd International Conference on Electronics and Communication Engineering (ICECE’2019), on 9-11 December 2019, Xi'an, China. 

[38]     S. W. Hussain ,T. V. Mahendra, S. Mishra, and A. Dandapat, " A Quasi-Static Storage and Decision Block for Performance-Efficient Content Addressable Memory ”, in 6th IEEE International Conference on Engineering Technologies and Applied Sciences (ICETAS), on 20-21 December 2019, Kuala Lumpur, Malaysia.

[37]         T. V. Mahendra, Sh. Wasmir Hussain, S. Mishray and A. Dandapat, ““Low Match-Line Voltage Swing Technique for Content Addressable Memory” (paper #1570538547),  in 7th International Conference on Smart Computing & Communications (ICSCC)] on 28-30 June 2019, Curtin University Malaysia, Miri, Malaysia.

[36]         T. V. Mahendra, Sh. Wasmir Hussain, S. Mishray and A. Dandapat, ““Performance Analysis of N-CAM, P-CAM and TG-CAM Using 45-nm Technology (Paper ID)ICICCS-045””,  in IEEE International Conference on Intelligent Computing and Control Systems [ICICCS 2019] on 15-17 May 2019, Tamilnadu, India.


[35]      S. Roy D. Kumar A. Dandapat P. Saha, “Discretized Sinusoidal Waveform Generators for Signal Processing Applications”,  in IEEE 2018 2nd International Conference on Trends in Electronics and Informatics (ICOEI) on 11-12 May 2018, Tirunelveli, India.

[34]    Farhana Begum, Sandeep Mishra, Md. Najrul Islam and Anup Dandapat, “Analysis and Proposal of A Flash Subranging ADC Architecture”,  in International Conference on Microelectronics, Computing & Communication Systems (MCCS-2018) on 12-13th May-2018, Ranchi.


[33]     D. Kumar, P. Saha, A. Dandapat, ‘‘A new Vedic division algorithm for binary number systems,’’ in 6th international conference on 'Computing, Communication and Sensor Network (CCSN), Kolkata, Dec. 2017.

[32]         S. Sarma, F. Begum and A. Dandapat, ‘‘Design of a 2.5 GS/s 6-bit 2.4 mW Flash ADC in 45-nm CMOS Technology,’’ in 2nd International Conference on Inventive Computation Technologies (ICICT), 2017, Coimbatore, pp. 1-6.

[31]       Venkatesh Mani Tripathi, Sandeep Mishra, Jyotishman Saikia, and Anup Dandapat, ‘‘A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access,’’ in 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), 2017, pp. 1-5.


[30]       Jyotishman Saikia, Sandeep Mishra, and Anup Dandapat, ‘‘Large Scale Dynamic Content Addressable Memory with Hybrid Matchline Structure,’’ in Students’ Technology Symposium (TechSym), 2016 IEEE, 2016. Received Best Paper Award.

[29]      Telajala Venkata Mahendra, Sandeep Mishra and Anup Dandapat, ‘‘Fully Dynamic High Density Associative Storage Architectures: Study, Comparison and a Proposal,’’ in Electronics and Communication Systems (ICECS), 2016 3rd International Conference on, 2016, pp. 1-4.


[28]        Vinay Kumar, Chandan Kumar Jha, Gaurav Thapa and Anup Dandapat, “Design of Low Power and High Speed Carry Look Ahead Adder (CLA) Using Hybrid CMOS Logic Style”, in International Conference on Micro Electronics Electromagnetics and Telecommunications ( ICMEET 2015), Visakhapatnam, Andhra Pradesh, India, Dec-2015.


[27]      Vinay Kumar, A. Dandapat, “Transistor Level Implementation of Cyclic Combinational Circuits”, in International Conference on Advances in Communication, Network, and Computing – CNC 2014, Chennai, India, Feb-2014.


[26]         Prabir Saha, Partha Bhattacharyya, Deepak Kumar and Anup Dandapat, “ASIC Implementation of High Speed Processor for Computing Fast Hartley Transformation”  in International Conference on Advanced Electronic Systems, CSIR-CEERI PILANI, Sep-2013.

[25]     Prabir Saha, Deepak Kumar, Partha Bhattacharyya and Anup Dandapat, “Reciprocal unit based on Vedic mathematics for signal processing applications”, in International Symposium on Electronic System Design (ISED), Singapore, Dec 2013.


[24]          Prabir  Saha,  Arindam  Banerjee,  Anup Dandapat  and  Partha  Bhattacharyya,  “ Design of High Speed Vedic Multiplier for Decimal number System” in VLSI Design & Test Symposium, 2012.


[23]         M. Chanda, A. Dandapat, H. Rahaman, “Pre-Settable Single Clocked Adiabatic Sequential Circuits for Ultra Low Power Architectures”, in 9th international conference on power electronics and Drive systems, 2011.

[22]        Prabir Saha, Arindam Banerjee, Partha Bhattacharyya and Anup Dandapat, “Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications” in International Symposium on Electronic System Design (ISED), 19-21 December 2011, Kochi, India, 2011.

[21]         M. Chanda, A. Dandapat, H. Rahaman ,“Design and Analysis of Tree-Multiplier using Single-Clocked Energy Efficient Adiabatic Logic”, in: Proceedings of the IEEE, Techsym, 2011. (Published in IEEE xplore)

[20]      Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat, “High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics”; in: Proceedings of the IEEE, Techsym, 2011. (Published in IEEE xplore)

Educational Qualifications

  • Ph.D (Engg) (Digital VLSI Design) from Jadavpur University in 2008

Courses Taught

1. Basic Electronics                                UG
2. Digital Design                                     UG
3. Semiconductor Devices                    UG/PG
4. Analog Integrated Circuits               UG
5. Digital Integrated Circuits                UG
6. VLSI Design                                        UG/PG
7. Fabrication Technology                    PG
8. Low Power VLSI                                 PG
9. Microprocessor                                 UG
10. VLSI Circuits and Systems             PG/UG
11. Computer Architecture                  UG
12. Digital VLSI Circuits                        UG/PG

Administrative Responsibility

  • Founder Assoc. Dean (Academics Affairs), from July, 2014-July, 2017
  • Founder Dean (Academics Affairs), from July, 2017-Oct, 2018
  • Founder HoD, ECE, from Jan, 2013-Jan, 2017
  • NKN Nodal Officer, from July, 2013-July 2017
  • Ranking Committee Chairman
  • Visvesvaraya PhD Co-ordinator

Work Experience

1)  Professor at NIT Meghalaya-Feb 23. 2024- till date.

2)  Associate Prof.,  H.O.D in ECE dept.  and 4 years as Associate Dean (Academics), Dean (Academics) [from July 2017-Oct 2018] at NIT Meghalaya-2012- 2024.

3)  Associate Prof./ H.O.D in ECE dept. at CITM-2011- 2012.

4)  Associate Prof. / H.O.D in ECE dept. at MIET-2010- 2011.

5)  Research Faculty at Jadavpur University-2007- 2010.

6)  Research Engineer at Jadavpur University-2006- 2007

7)  Lecturer: Jogesh Chandra Chaudhuri College-2004 – 2006

8)  Guest research instructor at BESU, Shibpur (IIEST)-1Year

9)  Guest faculty at Jadavpur University- 2 Years


        1.       Name   : Special Manpower Development Project

Funding Agencies            : Meity

Amount                             : 94.04 Lakh

Role                                    : Chief Investigator

Duration                            : 5 Years

Status                                 : Completed (Dec 2015-2021)

       2.   Name  : A “Study Project Proposal” on Dynamic Reconfigurable Implementation of Cryptographic Algorithms on FPGA Platform.

                Funding Agency                  : DeitY 

                Amount                              : 15 Lakh

                Role                                      : Co-Investigator

                Duration                              : 1 Year

                Status                                   : Completed (Jan 2016-Mar 2017)

       3.  Name   : Ultra Low Power Multi Array 64K X 16 Dual Bit Associative Memory with partial matching Capability.

                Funding Agency                   : DST-SERB

Amount                              : 26.3 Lakh

                Role                                       : Chief-Investigator

                Duration                              : 3 Years

                Status                                  : Completed (Mar 2016-Mar2019)

4.  Name : Assessment of climate change impact on soils and various water basins of Meghalaya using existing and newer techniques.

                Funding Agency                  : DST

Amount                             : 66.45 Lakh

                Role                                   : Co-Investigator

                Duration                           : 3 Years

                Status                                : Ongoing (Mar 2019-Mar2022)

Students Supervised/Supervising

  • Ph.D
  • Dibyendu Kayal, Ph.D, Study of Low Power High Performance Digital Circuits using Nano Scale MOS Structure, 2012
  • Prabir Saha, Ph.D, Efficient VLSI Implementation of Arithmetic Operations Based on Vedic Mathematics, 2014
  • Vinay Kumar, Ph.D, Circuit level optimization techniques for low power VLSI Design, 2017
  • Sandeep Mishra, Ph.D, High Density Ternary Content Addressable Memory : Storage and Sensing, 2018
  • Deepak Kumar, Ph.D, Implementation of the Computational Arithmetic Operations for Signal Processing Applications, 2019
  • Farhana Begum, Ph.D, Low-Power High-Resolution Flash-SAR ADC: Standalone and Hybrid Architectures, 2020
  • Telajala Venkata Mahendra, Ph.D, Precharge Free Content Addressable Memory : Binary and Ternary Storage , 2021
  • Sheikh Wasmir Hussain, Ph.D, Matchline controlled Content Addressable Memory: Low power and High speed Searching, 2022
  • M.Tech
  • Partha Bose, M.Tech, High performance and low power 16-bit binary squarer using dual threshold CMOS technology, 2007
  • Somdev Roy, M.Tech, Design of a High Speed Low Power Booth’s Multiplier, 2007
  • Rupam Das, M.Tech, Design and Comparison of High Speed and Low Power Parallel Adders, 2008
  • Prabir Saha, M.Tech, Design of High Speed Multi-bit Adders and its Application to Multipliers and Circular Convolution, 2008
  • Sudipta Ghosh, M.Tech, Comparative study of low power and high speed factorial circuit in different nano-meter regimes, 2010
  • Biswarup Mukherjee, M.Tech, Design of Combinational Circuit by using Cyclic Combinational Method, 2010
  • Debapriyo Ghosh, M.Tech, Design of Seven Segment Decoder using Cyclic Combinational Method and its Implementation in FPGA, 2011
  • Prakash Chandra Mondal, M.Tech, Design & ASIC implementation of cyclic combinational circuit by direct truth table method for low power VLSI, 2012
  • Telajala Venkata Mahendra, M.Tech, Design and Implementation of a High Performance Dynamic Associative Storage, 2016
  • Venkatesh Mani Tripathi, M.Tech, Design and Analysis of High Speed Voltage Sense Amplifier, 2016
  • Abishek Adarsh, M.Tech, Design of 2.5 GS/Sec Sub-Ranging ADC by using High Speed Analog Comparator, 2016
  • Abhinay Singh, M.Tech, Design of Low Power 8kb SRAM Chip in Cadence Tool using 45 Nanometer Technology, 2016
  • Sheikh Wasmir Hussain, M.Tech, Study and Comparative Analysis of Binary Comparator and Content Addressable Memory, 2017
  • Smita Sarma, M.Tech, Comparative Analysis of Low Power Static and Dynamic Comparator and Implementation of SAR-ADC, 2017
  • Md. Najrul Islam, M.Tech, Design and Implementation of High Performance, Low Power SRAM Array, 2018
  • Lopa Bhuyan, M.Tech, Comparative Study and Analysis of Custom IC Layout Design Styles, 2018
  • Abhishek Upadhyay, Design of an Efficient 64-bit Multiplier using Adaptive Compressors, 2019
  • V. Chandana, High speed adders using Logical Effort calculation, 2020
  • Vedanshu Kuwal, Analysis of the universal gates based on the comparative factors of delay propagation, average power dissipation & logical effort, 2021
  • Manolina Saha, Memory Design using CMOS Digital Neural Networks, 2021
  • Arundhati Dutta Gupta, Low Power Sense Amplifier for 64x32 Memory Array and Associative Module Design, 2022
  • Nivedita Chaurasia , Memory Design using CMOS Digital Neural Networks,2023
  • B.Tech
  • Supriya Das and Sweta Prasad, B.Tech, Design of low power content addressable memory (CAM), 2014
  • Arpit Shekhar and Shashi Kant, B.Tech, Implementation of real time traffic light signal using Microcontroller, 2014
  • Sumit Baidya and Prathana Gautam, B.Tech, A low power memory design for wire speed applications using ternary dual bit associative memory and cache, 2015
  • Rasalinda Diengdoh and Depphang Chyrmang, B.Tech, Design and Implementation of Different Low Power Adders, 2020
  • Banpynskhem Nongsiej, Bhukya Saikumar,Ravi Raj, B.Tech, Low Power Multipliers: Wallace tree, Serial-paralle, BAUGH WOOLEY multiplier, 2021.
  • Pankaj Singariya, Anurag Deori, Airilang Sohshang and Sweeta Hajong, B.Tech, seven segment Display interfacing with microcontroller in MPLAB, 2022.
  • Pujari Pushparaj Naik, B.Tech, LOW POWER DIGITAL SENSE AMPLIFIER, 2022.
  • Harshit Sagar, B.Tech, Microprocessor Based Security System, 2023
  • Konduru Hitesh Varma, Rithika Gudla, B.Tech, Content addressable memory (CAM) cell design,2023.




Ph.D selection Committee

Screening & Selection

Convocation preparation committee

Line-up the preparation

Library Committee

Selection of Library books, journals etc. (related to ECE)

Academic Progress Committee


Departmental Advisory Committee


Departmental Research Committee


Screening Committee for Student Free ship


National Institutional Ranking Framework (NIRF) committee, 2016/2017


Research Committee (till 2016)


Senate (till Oct 2018)

Dean (AA)

PG Programme Evaluation Committee (PGPEC) (till Oct 2018)


UG Programme Evaluation Committee (UGPEC) (till Oct 2018)


Conference/Symposium/Workshop/Seminar Organised


1)        International conference on Electronic Design, Computer Networks & Computer Aided Verification (EDCAV-2015) as organizing chair. 29-30 Jan, 2015.

2)        International Conference on Innovations in Electronics, Signal Processing and Communications (IESC-2017) as convenor.


1)     One day workshop on Tanner EDA Tools Training, jointly organized by Jadavpur University and Integrated Microsystem, 19th Jan, 2008, at Jadavpur University, Kolkata, India.

2)        Workshop on Schematic & Layout Design Flow in CADENCE, 16th – 18th Jan 2014, organized by ECE Dept, NIT Meghalaya.

3)        One day workshop on curriculum Development for B.Tech Programme on 19th Mar, 2018-as convenor.

4)        5-day refresher course on “Recent trends in VLSI Design” during 27th Sep-1st Oct 2021-as Organizing chair.

5)        5-day short term course on “Custom IC Design from Simulation and verification to Tape-out” during 16th-20th Sep 2021-as a convenor.

Short Term Course:

1)      Short term course on Electronic Design Automation & Digital Systems Realization using FPGA, organized by ECE Dept, NIT Meghalaya, 9th June to 9th July, 2014.

2)      Short term course on Custom IC Design Using Cadence Tools & HDL Synthesis and Implementation on FPGA. 6th-11th June 2016—as convener.

3)     Short Term Training Programme on Digital Design and Analysis at Backend Level Using CADENCE during 5th Mar-9th Mar, 2018—as convenor.

4)     5-day short term course on “Custom IC Design from Simulation and verification to Tape-out” during 16th-20th Sep 2021-as a convenor.

5)    5-day Training program on emerging technology: Robotic Process Automation (RPA) during 20th Mar-24th Mar 2023, in collaboration with CDAC-Kolkata-as a convenor.

Awards & Recognition

·         Received “Best Researcher-2016” award from NIT in 2017.

·         Received “Leader of the year-2015” award from NIT Meghalaya for best leadership role in 2016.

·         Received Young Faculty Research Fellowship from DeitY in 2016.

·         Elevated to Senior Member IEEE in 2015

·        Ranked in the Top 10 of the Cadence Design Contest 2005-2006 for the paper “Design and Power-Performance Optimization of a   Low Leakage Serial CAM”.

·        Received National Scholarship (Given by the Govt. of India, Human Resource Dept.) for the performance in UG.

·         Stood first position in Haldia Sub-Division in the Madhyamik Examination.